cy7c1381d 18Õ×루512KµÄ¡Á36£¯1M¡Á18£© Á÷ͨ¹ýSRAM

¡¡¡¡The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V£¬ 512K ¡Á 36 and 1M ¡Á 18 synchronous flow through SRAMs£¬ designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns £¨133 MHz version£©¡£ A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input £¨CLK£©¡£ The synchronous inputs include all addresses£¬ all data inputs£¬ address pipelining chip enable £¨CE1£©£¬ depth-expansion chip enables £¨CE2 and CE3£©£¬ burst control inputs £¨ADSC£¬ ADSP£¬ and ADV£©£¬ write enables £¨BWx£¬ and BWE£©£¬ and global write £¨GW£©¡£ Asynchronous inputs include the output enable £¨OE£© and the ZZ pin. The CY7C1381D/CY7C1383D/CY7C1383F allows interleaved or linear burst sequences£¬ selected by the MODE input pin. A HIGH selects an interleaved burst sequence£¬ while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe £¨ADSP£© or the cache controller address strobe £¨ADSC£© inputs. Address advancement is controlled by the address advancement £¨ADV£© input. Addresses and chip enables are registered at rising edge of clock when address strobe processor £¨ADSP£© or address strobe controller £¨ADSC£© are active. Subsequent burst addresses can be internally generated as controlled by the advance pin £¨ADV£©¡£ CY7C1381D/CY7C1383D/CY7C1383F operates from a +3.3 V core power supply while all outputs operate with a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. For a complete list of related documentation£¬ click here.