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¡¡¡¡The CY7C1371D/CY7C1373D is a 3.3 V£¬ 512K ¡Á 36/1M ¡Á 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371D/CY7C1373D is equipped with the advanced No Bus Latency £¨NoBL£© logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM£¬ especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable £¨CEN£© signal£¬ which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns £¨133-MHz device£©¡£ Write operations are controlled by the two or four byte write select £¨BWX£© and a write enable £¨WE£© input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables £¨CE1£¬ CE2£¬ CE3£© and an asynchronous output enable £¨OE£© provide for easy bank selection and output tristate control. To avoid bus contention£¬ the output drivers are synchronously tristated during the data portion of a write sequence. For a complete list of related documentation£¬ click here.