Reducing DC Errors in Op Amps (A

¡¡¡¡Abstract. An IC op amp design that reduces bias currents below 100 pA over a b55¡ìC to a125¡ìC temperature range is discussed. Super-gain bipolar transistors with on-wafer trimming are used£¬ providing low offset voltage and drift. The key to low bias current is the control of high temperature leakage currents along with the development of reasonably accurate nanoampere current sources with low parasitic capacitance. introduction A bipolar replacement for the LM108 £Û1£Ý drastically reduces offset voltage£¬ bias current and temperature drift. This design£¬ the LM11£¬ does not depend on new technology. Instead£¬ the improvements result from a better understanding of transistor behavior£¬ new circuit techniques and the application of proven offset trimming methods. Table I summarizes the results obtained. The combination of low offset voltage and low bias current is unique to IC op amps£¬ while the performance at elevated temperatures represents an advance in the state of the art. TABLE I. Input error terms of the LM11 show an improvement over FET op amps even at room temperature. There is little degradation in performance from b55¡ìC to 125¡ìC. Other important specifications are somewhat better than LM108A.