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About this Quick Reference Guide

Digital logic designers today must create designs consisting of tens-ofthousands
of gates while meeting increased pressure to shorten time-tomarket.
At the same time, designers must maintain architectureindependence
without sacrificing silicon efficiency.
Meeting these requirements with today¡¯s EDA software tools is not easy.
Schematic-based design entry provides superior efficiency but
implements architecture-dependent, low-level functions. High-level
hardware description languages (HDLs) offer architecture-independence,
but offer reduced silicon efficiency and performance.
Because a standard set of functions supported by all EDA and integrated
circuit (IC) vendors was not previously available, bridging the gap
between architecture-independence and efficiency was difficult.
However, with the introduction of EDA software tools that support the
library of parameterized modules (LPM), designers can now create
architecture-independent designs that have high silicon efficiency.